Designers of communication systems have often used multi-phased, low-frequency clocks to sample high-speed data streams in phase-locked loop (PLL)-based clock and data recovery circuits (CDRs). One advantage to using such systems is that traditional bang-bang phase detector circuits can be used at relatively low clock frequencies. For example, it is well described in the relevant literature to use a four-phased clock to cause four separate phase detectors to sample an incoming data stream. The outputs of the four phase detectors are then continuously updated at the based clock frequency to form a sequence of data words. The data words, in turn, are converted to analog form using a digital-to-analog (DAC) converter and used to control a voltage-controlled oscillator (VCO).
Unfortunately, the above-described system requires the use of a DAC having a relatively large number of bits while operating at a very high frequency. While it is possible to use individual DACs (typically 1.5 bits) for each phase-detector, this approach requires that signal addition occur in the analog domain and that phase error information be elongated for an undesirable length of time. While this problem may be corrected using time-domain multiplexing circuitry to combine consecutive phase-error signals into a single stream, this approach requires that the DAC and other circuitry operate at high frequencies, which as stated above can be difficult to implement.
Thus, new technology directed to improving clock recovery circuits is desirable.